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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Logic Switching Characteristics
Table 23: ILOGIC Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
Setup/Hold
T ICE1CK /T ICKCE1
T ISRCK /T ICKSR
T IDOCKE2 /T IOCKDE2
CE1 pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without
Delay (HP I/O banks only)
0.42/0.00 0.48/0.00 0.67/0.00 0.67/0.00 0.56/–0.16
0.53/0.01 0.61/0.01 0.99/0.01 0.99/0.01 0.88/–0.30
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.41
ns
ns
ns
T IDOCKDE2 /T IOCKDDE2 DDLY pin Setup/Hold with respect to CLK
(using IDELAY) (HP I/O banks only)
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.01/0.41
ns
T IDOCKE3 /T IOCKDE3
D pin Setup/Hold with respect to CLK without
Delay (HR I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.41
ns
T IDOCKDE3 /T IOCKDDE3 DDLY pin Setup/Hold with respect to CLK
(using IDELAY) (HR I/O banks only)
Combinatorial
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.01/0.41
ns
T IDIE2
T IDIDE2
T IDIE3
T IDIDE3
D pin to O pin propagation delay, no Delay
(HP I/O banks only)
DDLY pin to O pin propagation delay (using
IDELAY) (HP I/O banks only)
D pin to O pin propagation delay, no Delay
(HR I/O banks only)
DDLY pin to O pin propagation delay (using
IDELAY) (HR I/O banks only)
0.09
0.10
0.09
0.10
0.10
0.11
0.10
0.11
0.12
0.13
0.12
0.13
0.12
0.13
0.12
0.13
0.14
0.15
0.14
0.15
ns
ns
ns
ns
Sequential Delays
T IDLOE2
T IDLODE2
T IDLOE3
T IDLODE3
T ICKQ
T RQ_ILOGICE2
T GSRQ_ILOGICE2
T RQ_ILOGICE3
T GSRQ_ILOGICE3
D pin to Q1 pin using flip-flop as a latch without
Delay (HP I/O banks only)
DDLY pin to Q1 pin using flip-flop as a latch
(using IDELAY) (HP I/O banks only)
D pin to Q1 pin using flip-flop as a latch without
Delay (HR I/O banks only)
DDLY pin to Q1 pin using flip-flop as a latch
(using IDELAY) (HR I/O banks only)
CLK to Q outputs
SR pin to OQ/TQ out (HP I/O banks only)
Global Set/Reset to Q outputs
(HP I/O banks only)
SR pin to OQ/TQ out (HR I/O banks only)
Global Set/Reset to Q outputs
(HR I/O banks only)
0.36
0.36
0.36
0.36
0.47
0.84
7.60
0.84
7.60
0.39
0.39
0.39
0.39
0.50
0.94
7.60
0.94
7.60
0.45
0.45
0.45
0.45
0.58
1.16
10.51
1.16
10.51
0.45
0.45
0.45
0.45
0.58
1.16
10.51
1.16
10.51
0.54
0.55
0.54
0.55
0.71
1.32
11.39
1.32
11.39
ns
ns
ns
ns
ns
ns
ns
ns
ns
Set/Reset
T RPW_ILOGICE2
T RPW_ILOGICE3
Minimum Pulse Width, SR inputs (HP I/O
banks only)
Minimum Pulse Width, SR inputs (HR I/O
banks only)
0.54
0.54
0.63
0.63
0.63
0.63
0.63
0.63
0.68
0.68
ns, Min
ns, Min
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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